1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically to a structure of a semiconductor memory device having a so-called a stacked capacitor cell as a charge storing portion.
2. Description of the Background Art
Recently, semiconductor memory devices are in great demand, as information devices such as computers have come to be widely used. Especially, semiconductor memory devices having larger memory capacitances and higher reliability have come to be increasingly desired. Under such circumstances, various developments have been made for increasing degree of integration and improving reliability of the semiconductor memory devices. DRAM (Dynamic Random Access Memory) is one of the semiconductor memory devices, which is capable of random input/output of memory information. Generally, a DRAM comprises a memory cell array which is a memory region for storing a number of memory information and peripheral circuits necessary for external input/output.
FIG. 4 is a block diagram showing a structure of a common DRAM. Referring to FIG. 4, a DRAM 50 comprises a memory cell array 51 for storing data signals of memory information, a row and column address buffer 52 for externally receiving address signals A.sub.0 to A.sub.9 for selecting a memory cell constituting a unit memory circuit, row decoder 53 and column decoder 54 for designating the memory cell by decoding the address signal, a sense refresh amplifier 55 for amplifying and reading a signal stored in the designated memory cell, data in buffer 56 and data out buffer 57 for inputting/outputting data, and a clock generator 58 for generating clock signals serving as control signals to respective portions.
The memory cell array 51 occupying a large area on a semiconductor chip is formed of an array of a plurality of memory cells each storing unit memory information. FIG. 5 is an equivalent circuit diagram of 4 bits of memory cells constituting the memory cell array 51. The memory cell array 51 comprises a plurality of word lines 1a, 1b, 1c and 1d extending in parallel with each other in row direction and a plurality of bit line pairs 2a and 2b extending in parallel to each other in column direction. Memory cells are formed in the proximity of intersections between the word lines 1a to 1d and the bit lines 2a and 2b. The memory cell 3 is formed of 1 MOS (Metal Oxide Semiconductor) transistor 4 and 1 capacitor 5. The arrangement such as shown in FIG. 5 in which a pair of bit lines 2a and 2b are arranged in parallel to each other on a side of a sense refresh amplifier 55 is called a folded bit line type structure.
A planar layout of the DRAM in the range shown in the equivalent circuit diagram of FIG. 5 is shown in FIG. 6. Four memory cells are shown in FIG. 6. The respective memory cells are formed of a set of MOS transistors Q1, Q2, Q3 and Q4 and capacitors Cs1, Cs2, Cs3 and Cs4 formed in operational regions A1, A2, A3 and A4. Gate electrodes constituting the transistors Q1 to Q4 are formed of portions of word lines 1a to 1d corresponding to the respective memory cells. Bit lines 2a and 2b are formed above the word lines 1a to 1d insulated from and intersecting with the word lines 1a to 1d. The bit lines 2a and 2b are connected to the memory cells through contact holes C1, C2 and C3.
A cross sectional structure of the memory cells taken along the line VII--VII of FIG. 6 is shown in FIG. 7. 2 bits of memory cells 3, 3 are shown in FIG. 7. The memory cell 3 is formed 1 MOS transistor 4 and a capacitor 5. The MOS transistor 4 comprises a pair of source.drain regions 6, 6 formed spaced apart from each other on a surface of silicon substrate 40 and a gate electrode 8 (1b, 1c) formed on the surface of the silicon substrate 40 with a gate oxide film 7 posed therebetween. The capacitor 5 comprises a lower electrode (storage node) 9 connected to one of the source.drain regions 6,6 of the MOS transistor 4, a dielectric layer 10 formed on the upper surface of the lower electrode 9 and an upper electrode (cell plate) 11 covering the upper surface of the dielectric layer 10. The lower and upper electrodes 9 and 11 are formed of, for example, polycrystalline silicon. Such a capacitor having a stacked structure is called a stacked capacitor. The stacked capacitor 5 has one portion extending to an upper portion of the gate electrode 8 with an insulating film 12 posed therebetween, and the other portion extending to an upper portion of a field oxide film 13. The surface of the silicon substrate 40 on which the capacitor 5 and so on are formed is covered with a thick interlayer insulating film 14. The bit line 2b passing through the upper portion of the interlayer insulating film 14 is connected to the other one of the source.drain regions 6 of the MOS transistor 4 through a contact hole 15.
A method of manufacturing a memory cell of a conventional DRAM will be described in the following with reference to FIGS. 8A to 8E.
First, as shown in FIG. 8A, a field oxide film 13 for isolating elements formed of a silicon oxide film, for example, is formed on the silicon substrate 40. Consequently, an active region 16 for forming elements is provided on the surface of the silicon substrate 40.
Thereafter, referring to FIG. 8B, a gate electrode 8 is formed on the active region with a gate oxide film 7 posed therebetween, and at the same time, a word line 1d is formed on a prescribed position of the field oxide film 13. A pair of impurity regions having lower concentration are formed in the silicon substrate 40 using the gate electrode 8 as a mask. Then, the gate electrode 8 and the surroundings of the word line 1d are covered with an insulating film 12. Then, impurities are introduced into the silicon substrate 40 by using the gate electrode 8 covered with the insulating film 12 as a mask, to form the source.drain regions 6, 6 having higher impurity concentration.
Thereafter, referring to FIG. 8C, a polycrystalline silicon layer is deposited on the entire surface of the silicon substrate 40. Thereafter, the polycrystalline silicon layer is patterned to a prescribed shape. BY doing so, the lower electrode 9 extending from the upper portion of the gate electrode 8 to the upper portion of the filed oxide film 13 and electrically connected to one of the source.drain regions 6 is formed.
Thereafter, referring to FIG. 8D, the dielectric layer 10 of a silicon nitride film and an upper electrode 11 formed of polycrystalline silicon are formed on the surface of the lower electrode 9.
Finally, referring to FIG. 8E, a thick interlayer insulating film 14 is formed. A contact hole 15 is formed at a prescribed the position and thereafter the bit line 2b is formed. Consequently, the bit line 2b is connected to the other one of the source.drain regions 6 of the MOS transistor 4. Through the above described steps, the memory cell 3 of a DRAM is manufactured.
Generally, the charge storing capacitance of the capacitor 3 is in proportion to the opposing areas of the lower electrode 9 and the upper electrode 11 facing to each other with the dielectric layer 10 posed therebetween. Therefore, the opposing areas should be increased in order to increase the capacitance of the capacitor 3. However, as described above, the device structure of DRAM has been continuously reduced in size. Planar area of occupation in the memory cell structure has been reduced in order to improve the degree of integration. For this purpose, the planar area of occupation of the capacitor has been limited and reduced. The reduction of the opposing areas between the electrodes of the capacitor 5 and accordingly, the reduction of the capacitance of the capacitor cause the following drawbacks.
(a) When the capacitance of the capacitor 5 is reduced, the amount of signal reading from the capacitor 5 is also reduced. Consequently, the sensitivity to the memory signals is reduced, degrading the reliability of the DRAM.
(b) Malfunctions tend to occur by the generation of soft errors induced by .alpha. lay.
Therefore, the reduction of the capacitor capacitance leads to essential degradation of the function of the DRAM, causing serious problems.
Structures shown in FIGS. 9 and 10 have been proposed to increase the capacitance of the capacitor.
The capacitor shown in FIG. 9 is described in detail in "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node in STC DRAM Cell" by T. Kisu, et al. 20th International Conference on Solid State Devices and Materials, 1988, pp. 581-584. The capacitor 5 comprises a lower electrode 9 having two polysilicon layers partially stacked spaced apart from each other. The dielectric layer 10 and the upper electrode 11 are formed to cover the concave and convex surfaces of the two-layered lower electrode 9.
The capacitor shown in FIG. 10 is described in detail in "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M and 64M DRAMS" by T. Ema, et al, IEDM 88, pp. 592-595. The capacitor 5 comprises a lower electrode 9 formed to have a plurality of fins. The dielectric layer 10 and the upper electrode 11 are formed along the fin shaped portion of the lower electrode 9.
The above described two capacitors are adapted to increase capacitance of the capacitors by forming the surface of the lower electrode 9 with fins and accordingly, by increasing the opposing areas between the lower and upper electrodes 9 and 11.
However, the idea of effectively using the surface area of the impurity region as a portion of the capacitor is not disclosed in either of the above described capacitors.